1. Field of the Invention
The present invention generally relates to nonvolatile FeRAM (ferroelectric random access memory) control devices, and more specifically, to a nonvolatile FeRAM control device where a programmable register can be stably driven when a power voltage is boosted in a low voltage region.
2. Description of the Related Art
Generally, a ferroelectric randaom access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not low even after eliminating an electric field applied thereto.
FIG. 1 is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance.
A polarization induced by an electric field does not vanish but remains at a certain portion (‘d’ or ‘a’ state) even after the electric field is cleared due to existence of a residual (or spontaneous) polarization. The FeRAM cell is used as a memory device by corresponding the ‘d’ and ‘a’ states to binary values of ‘1’ and ‘0’, respectively.
FIG. 2 is a structural diagram illustrating a unit cell of the conventional FeRAM device.
The unit cell of the conventional FeRAM is provided with a bitline BL arranged in one direction and a wordline WL arranged in another direction vertical to the bitline BL. A plateline PL is arranged parallel to the wordline WL and spaced at a predetermined interval.
The unit cell is also provided with a transistor T1 having a gate connected to an adjacent wordline WL and a source connected to an adjacent bitline BL. A drain of the transistor T1 is connected to one terminal of a ferroelectric capacitor FC0. The other terminal of the ferroelectric capacitor FC0 is connected to the plateline PL.
The data input/output operation of the conventional FeRAM is now described referring to FIGS. 3a and 3b. 
FIG. 3a is a timing diagram illustrating a write mode of the conventional FeRAM.
When entered into an active period, a chip enable signal CEB applied externally transits from a high to low level. If a write enable signal WEB simultaneously transits from a high to low level, the cell array is enabled to start a write mode. Thereafter, when an address is decoded in the write mode, a pulse applied to a corresponding wordline transits from a “low” to “high” level, thereby selecting the cell.
In the interval where the wordline WL is held at a high level, a high signal of a predetermined interval and a low signal of a predetermined interval are alternatively applied to a corresponding plateline PL. In order to write binary logic values ‘1’ or ‘0’ in the selected cell, ‘high’ or ‘low’ signals synchronously with respect to the write enable signal are applied to a corresponding bitline BL. Here, a sense amplifier enable signal SEN is maintained at a high level.
In other words, when a high signal is applied to a bitline BL and a low signal is applied to a plateline PL, a logic value “1” is written as input data in the ferroelectric capacitor FC0. When a low signal is applied to a bitline BL and a high signal is applied to a plateline PL, a logic value “0” is written as input data in the ferroelectric capacitor FC0.
FIG. 3b is a timing diagram illustrating a read mode of the FeRAM.
When entered into an active period, a chip enable signal CEB externally transits from a “high” to “low” level. All bitlines are equalized to a “low” level by an equalization signal before selection of a required wordline WL.
After each bitline is inactivated and an address is decoded, the required wordline WL is transited from a “low” to “high” level by the decoded address, thereby selecting a corresponding unit cell. A “high” signal is applied to a plateline PL of the selected cell to destroy data Qs corresponding to the logic value “1” stored in the FeRAM.
If the logic value “0” is stored in the FeRAM, its corresponding data Qns will not be destroyed. In this way, the destroyed and non-destroyed data output different values, respectively, according to the above-described hysteresis loop characteristics.
In other words, as shown in the hysteresis loop of FIG. 1, the state moves from the ‘d’ to ‘f’ when the data is destroyed while the state moves from ‘a’ to ‘f’ when the data is not destroyed. As a result, the sense amplifier is enabled by the sense amplifier enable signal SEN after the lapse of a predetermined time. When the data is destroyed, the sense amplifier outputs a logic value “1” as output data DOUT. However, when the data is not destroyed, the sense amplifier outputs a logic value “0” as output data DOUT.
After the sense amplifier amplifies the data, the data should be recovered into the original data. Accordingly, the plateline PL is inactivated from “high” to “low” at the state whereby a ‘high’ signal is applied to the required wordline WL.
In the conventional nonvolatile FeRAM, metal/poly silicon (Poly-Si) wirings are used in a redundancy operation. However, an erroneous wiring cannot be restored to the original state because a laser cutting is used in the conventional redundancy operation. Moreover, the reliability of conventional FeRAM chips is degraded because it is impossible to exactly regulate reference levels for controlling cell data.
A method for regulating redundancy and reference levels of memory cells using a programmable unit register has been disclosed in order to overcome the above-described problems. However, the conventional programmable unit register controls a register by using an external power voltage VCC other than a pumping voltage VPP.
Generally, the programmable unit register is known to normally operate in a high voltage region above 1.0V. According to a power voltage boosting method, operation margin of the programmable unit is required to be secured in a low voltage region below 1.0V. When the conventional programmable unit register continuously operates at a pumping voltage VPP, power is consumed too much while generating the pumping voltage VPP. Accordingly, a circuit using a pumping voltage VPP with much less power consumption is disclosed in the present invention.